Sandro Bartolini graduated in "Computer Engineering" cum
laude at the Università di Pisa, where he got his PhD in "Computer
Science and Engineering" in 2003.
Since October 2002 he is an assistant professor (Ricercatore) at the Faculty of Engineering of the Università di Siena.
- Computer architecture: cache and memory hierarchy optimization, feedback-driven compiler optimizations, multi-core architectures, reconfigurable architectures, application and operating system characterization, embedded systems, low-power architectures, processor architecture and micro-architecture, performance evaluation.
- Security and cryptography: traditional, elliptic-curve crypto-systems for mobile and general-purpose architectures, instruction-set extensions, software optimizations.
- Multimedia: characterization of image and video applications.
(2010-2013) Main investigator of the Siena research group within
project PHOTONICA - Photonic Interconnect Technology for Chip
Multiprocessing Architectures. Partners: Università di Ferrara (coord.), Università di Siena, Politecnico di Bari.
Funded by the Italian Ministry of University and Research. FIRB Futuro in Ricerca program for young researchers.
(2010-2013) Participant to the FP7 Ip project TERAFLUX - Exploting dataflow parallelism in Teradevice Computing.
(2010-2012) Participant to the FP7 Strep project ERA - Embedded Reconfigurable Architecture.
(2009-2012) Participant to the FP7 Network of Excellence HiPEAC-2 - High Performance Embedded-System Architecture and Compilation.
(2010 - 4 months) Responsible of a R&D industrial project for RAI - Radio Televisione Italiana, within the ATLAS - Automatic Translation into Sign Language project, on the definition of a flexible and extensible meta-language for representing the LIS language ("Lingua Italiana dei Segni", i.e. Italian Sign Language) inside a computer device (e.g. PDA, PC, Digital Television).
- Workshop and tutorial chair of the Int.l Conf. on High Performance and Embedded Architectures and Compilers 2010, Pisa, Italy
- 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 editions of the International Workshop (ACM ISBN) on "MEmory performance: DEaling with Applications, systems and architecture" (MEDEA), held with the IEEE/ACM International Conference on "Parallel Architectures and Compilation Techniques (PACT)"
- Co-organizer and financial and local arrangement co-chair of the International Workshop on the
Arithmetic of Finite Fields (WAIFI 2008), Siena, Italy
Program committee membership:
- IEEE Int.l Conf. on High Performance Computing and Communications 2010
- ACM Symposium on
Applied Computing - Embedded Systems Track 2010, 2009, 2008, 2007,
2006, 2005, 2004, 2003
“We can't solve problems by using the same kind of thinking we used when we created them”