Roberto Giorgi – CURRICULUM VITAE - December 2008
|
Web: www.dii.unisi.it/~giorgi, Email: giorgi@unisi.it, Tel. 0577-191-5182. Professional Societies: Senior Member IEEE since 2003, IEEE Computer Society, ACM: SIGARCH (Computer Architecture), SIGMICRO (Microarchitecture), SIGBED (Embedded Systems). |
|
University Positions
· ASSOCIATE PROFESSOR at the Department of Information Engineering, University of Siena, Italy, since October 1st 2006.
· Assistant Professor with Tenure at the Department of Information Engineering, University of Siena, Italy, from March 15th 1999 to September 30th 2006.
· Post-Doctoral position at University of Alabama in Huntsville, AL, U.S.A., from February 1, 1999 to January 30th, 2000.
· National Science Foundation (NSF) research support, grant #9805216 regarding “Post-Doctoral Experimental Research for the Evaluation of Multithreaded Architectures” at University of Alabama in Huntsville, AL, U.S.A., during year 1999.
· Italian National Research Council (CNR) support, grant #203.15.9, for studying at University of Alabama in Huntsville, AL, U.S.A. during year 1999.
· Visiting Scholar at the Univ. of Belgrade, Serbia, Yugoslavia, May 2 to 16, 1998.
· Visiting Scholar at the Univ. of Texas in Arlington, TX, U.S.A., Jul. 23 to Aug. 30, 1997.
· Visiting Scholar at the Univ. of Washington, Seattle, WA, U.S.A. July 14 to Aug. 31, 1996.
Education and Professional Titles
· Research Doctorate (Ph.D.) in “Information Engineering: Electronics, Informatics, Telecommunications”, University of Pisa, March 16, 1999. Dissertation on “Evaluation of a Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Multithreaded Multiprocessors”.
· Professional Qualification as Engineer, through State Exam in the II Session of 1995, University of Pisa.
· Master of Engineering in Electronics, University of Pisa, July 19, 1995. Thesis on “Performance Evaluation of Multiprocessor Systems, based on Real Traces Analysis”. Mark:110/100 Magna cum Laude.
· High-School Diploma in Scientific Curriculum, Lyceum “Barsanti e Matteucci”, Viareggio, LU, Italy. Mark: 60/60.
Other Awards
· FORUM P.A./CNIPA Award by Italian Ministry of Innovation and Technologies for the best action to accessibility of public administration by the disable through the project “BlueSign Translator” (May 2006).
· IEEE Award (5th worldwide price 2000 $) for course projects, IEEE Computer Science International Design Competition (CSIDC) 2002 - (http://computer.org/csidc) for the realization of vice to Sign Language Translator based on Bluetooth Technology for helping the Deaf. January-June 2002
Teaching Activity
· Doctoral School in Information Engineering, S. Chiara College, University of Siena
- 2008/07, 07/06, "Low Power Architectures", Ph.D. level
· Master and Bachelor Degrees at Faculty of Engineering, University of Siena:
- 2009/08, 2008/07, 06/07, 05/06, 04/05, “Advanced Computer Architecture”, Master Level.
- 2009/08, 2008/07, 06/07, 05/06, 04/05, 03/04, 02/03, 01/02, 00/01, 99/00 - “Computer Architecture”, Bachelor Level.
- 2003/04 - “Embedded System Design”, Master Level.
- 2003/04, 02/03, 01/02 - “Informatics for Industrial Applications”, Bachelor Level.
- 2003/04, 02/03, 01/02 - “Advanced Computer Architecture”, 5-year Master Level.
- 2003/04 - “C++ Programming Laboratory”.
- 2002/03, 01/02 - “Computer Architecture Laboratory”
- 2000/01, (99/00 teaching assistant)-“Computer Architecture”, 5-year Master.
· Master in Digital Economy and E-business (E2C) of the University of Siena, in cooperation with Accenture, Cisco, IBM, Microsoft, Monte dei Paschi di Siena:
- 2003/04, 02/03 - “Programming Fundamentals”.
· Master in Management of Financial Institution and New Information Technologies of the University of Siena, in cooperation with Monte dei Paschi di Siena and Engineering:
- 2008/07, 06/07, 05/06 - “Information Security”.
- 2004/05, 03/04, 02/03, (00/01 co-teaching) - “Operating Systems and Security”.
- 2001/02, 00/01 - “Data-Base Management Systems”.
Other Teaching Activity
· Tutoring of Ph.D. student Nikola Puzovic, ciclo XXI, from November 2005 to September 2009.
· Tutoring of Ph.D. student Zdravko Popovic, ciclo XXI, from November 2005 to September 2009.
· Tutoring of Ph.D. student Paolo Bennati, ciclo XX, from November 2004 to September 2008.
· Co-Tutoring of Ph.D. Student Irina Branovic, years 2001-2004, since November 2001.
· Tutoring of student with grant Nenad Korolija, from February 2008 to September 2008.
· Tutoring of student with grant Roberto D'Aprile, from February 2008 to September 2008.
· Tutoring of student with grant Zdravko Popovic, from September 2004 to October 2005.
· Orientation Activity for potential students coming from High School.
· Tutor for several Master Thesis, Faculty of Engineering, University of Siena.
Educational Software freely available
§ The BASICRYPT BENCHMARK-SUITE http://www.dii.unisi.it/~giorgi/basicrypt
§ The WEBMIPS: Web-based MIPS simulator http://www.dii.unisi.it/~giorgi/WEBMIPS
§ JCACHESIM cache+cpu web-based simulator http://www.dii.unisi.it/~giorgi/jcachesim
University Service
· President of the Self-Evaluation Committee (RAV) for the Information Engineering Laurea (2006).
· Member of Ph.D. Committee, Department of Information Engineering, since April 2002.
· Member of Orientation and Tutoring Commission, from October 2001 to November 2005.
· Member of Local Area Network Management of Department Information Engineering, May 2001.
· Member of the Evaluation Board for PhD Program (Department of Information Engineering, Siena): 2002-present
· Member of the Evaluation Board for Master and Bachelor Degree in Computer Engineering (Faculty of Engineering, Siena): Feb_2006-present
· Member of the Evaluation Board for Master in New Technologies and Company Management (University of Siena): 2001-present.
· Member of Commission for ING-INF/05 (Computer Systems) call for researchers, Oct. 2005.
· Design and Maintenance of Orientation WEB Site, Faculty Engineering, Siena, Italy.
· Member of the group for Department LAN management since May 2001.
· Member of the Orienatation and Tutoring commission October 2001 to October 2005.
· Design and Maintanance Orientation web sites ( www.ing.unisi.it/orientamento , www.ing.unisi.it/orientamento/initinere , www.ing.unisi.it/orientaing ).
SERVICE TO THE INTERNATIONAL SCIENTIFIC COMMUNITY
· Independent Expert of the European Commission for the evaluation of Call FET (Future and Emerging Technology) 2008 - FP7 (7th Framework Programme) Massive ICT. FP6 IST-FET-26825 SHAPES (Scalable Software Hardware Architecture Platform for Embedded Systems), November 2006.
· Consultant for the EU Call Objective ICT-2009.8.1: FET proactive 1: Concurrent Tera-device Computing, Brussels, Nov. 2008.
· IEEE Judge (among the 8 coming from the Industry and the Academy) for IEEE Computer Science International Design Competition (CSIDC) 2001 (http://computer.org/csidc) sponsored by Intel, Toshiba, Ericsson, AMD, Microsoft, Lucent, EMC, Hewlett-Packard, Sun, Motorola, to assign prizes for 70000$. June-July 2001.
· Journal Reviewer: IEEE Transaction on Computers, IEEE Transaction on Parallel and Distributed Systems, IEEE Micro, IEEE Concurrency, Computer Journal, Journal of System Architecture, IEEE Transaction on Circuits and Systems.
· Conference Reviewer: ICCD, Computing Frontiers, HiPEAC, EuroPAR, DAC, IPPS, PACT, ACM-SAC, PDES, ESA, ISCC, Didamatica, Workshop WMPI, MEDEA, SCOPES, MULTIPROG.
· Reviewer of NWO Projects (Netherlands Research Organization) and EU projects.
COOPERATION WITH THE COMPANIES AND INSTITUTIONS
· Cooperation agreement with RAI (RADIOTELEVISIONE ITALIANA) for the implementation of advanced solutions for the integration of automatic translation systems of Sign Language for the Deaf in the television.
· Cooperation with Italian Association for the Education of the Deaf (AIES, Associazione Italiana Educazione Sordi) to support the study of a multimedial system for communicating in Italian Sign Language (LIS, Lingua Italiana dei Segni), years 2003-present.
· Contract for “Performance Evaluation of Coherence Protocols for Single-Chip Embedded Multiprocessors” at the Department of Information Engineering, University of Pisa. November 1998-January 1999.
· Contract for “Performance Evaluation of Multiprocessor System under Different Software Workload” at the Department of Information Engineering, University of Pisa. September-December 1995.
· Cooperation with VLSI Tech. Inc., San Jose, CA, U.S.A. to support the realization of X/MOTIF Graphical Interface for the commercial software “Charm - JumpStart 3.0”. September-October 1995.
Coordinamento di Iniziative Didattiche e Scientifiche
· Program Committee Member of Computing Frontiers 2009 www.computingfrontiers.org
· Financial/Local Co-Chair WAIFI-08, Workshop on Arithmetic of Finite Fields, Siena July 2008 www.waifi.org
· Program Committee Member of International Conference in Computer Design (IEEE-ICCD) 2008 www.iccd-conference.org/2008/
· Program Committee Member of IEEE SEC International Symposyum on Embedded Computing 2008 conference.cs.cityu.edu.hk/sec08/
· Co-Guest Editor of Journal of Embedded Computing, 2006 special issue on Embedded Single-Chip Multicore Architectures and related research - from System Design to Application Support, www.dii.unisi.it/~giorgi/jec-esc-mca/.
· Program Committee Member of International Conference HiPEAC 2006, 2005 (High Performance Embedded Architectures & Compilers), www.hipeac.net/hipeac/hipeac2005/.
· Program Committee Member of MULTIPROG 2009, 2008 (Programmability Issues for Multi-Core Computers) multiprog.ac.upc.edu
· Program Committee Member of International Workshop MEDEA 2008, 2007, 2006, 2005, 2004, 2003, 2002, 2001, 2000 tenuto congiuntamente alla conferenza PACT (Parallel Architecture and Compilation Techniques), garga.iet.unipi.it/medea05.
· Vice-chair of Comitato di Programma di International Conference ESA 2005 (Embedded Systems and Applications), juliet.stfx.ca/~lyang/esa-05/.
· Program Committee Member of International Workshop IEEE/IFIP-PDES 2005 (Parallel and Distributed Embedded Systems), juliet.stfx.ca/~lyang/icpads05-pdes/.
· Program Committee Member of di International Workshop SCOPES 2005 (Software and Compilers for Embedded Systems), www.scopesconf.org/.
· Program Committee Member of ACM-SAC, Embedded System Track 2006, 2005, 2004, 2003, www.ing.unipi.it/sac06/.
· Program Committee Member of PACT-2002 (Parallel Architecture and Compilation Techniques), www.pactconf.org
· Coordinator of Information Technology Courses for “Master of Management of Financial Institutions and New Information Technologies – GINTS-2002, GITS-2001 (http://www.unisi.it/gints) organized for Graduate Students in Engineering and Economy, Siena, Italy.
· Co-Guest Editor of ACM Computer Architecture News (official Newsletter of ACM Special Interest Group on Computer Architecture), number of December 2001, with emphasis on Compilation Techniques, Parallel Architectures and Frontiers Topics.
· Guest Editor of IEEE-TCCA NEWSLETTER (official Newsletter of IEEE Special Interest Group in Computer Architecture), number of January 2001, with emphasis on MEmory DEcopupled Architectures in modern microprocessors.
· Organization of MEDEA-2001 workshop (MEmory DEcoupled Architectures), international conference PACT-2001 (Parallel Architectures and Compilation Techniques), Barcelona, Spain, September 2001.
· Founder and Organizer of MEDEA-2001 MEDEA-2000 workshop (MEmory DEcoupled Architectures), PACT-2000 International Conference (Parallel Architectures and Compilation Techniques), Philadelphia, PA, U.S.A., October 2000.
COORDINATION AND PARTICIPATION TO RESEARCH PROJECTS
· 2008-2009, Coordinator and Principal Investigator “Monte dei Paschi di Siena Foundation”, “Integration of Sign Language for the Deaf in the digital television”, 50 K-EURO.
· 2007-2008, Recipient of funding from Regione Toscana (through National Association of the Deaf) for a project for the extension of the digital vocabulary of an automated Sign Language System for the Deaf, 10 K-EURO.
· 2008-2012, Participation to European Network of Excellence (NoE), Seventh Framework Program (FP7), “HIPEAC2: High-Performance Embedded Architecture and Compilation”, coordination University of Ghent, founding 4.8 M-EURO. http://www.hipeac.net/
· 2008, Coordinator of HiPEAC research cluster: Multithreaded Dataflow Architectures http://www.hipeac.net/node/2017; 10240 euro.
· 2008, Coordinator of HiPEAC research cluster: Cache implications of non-blocking thread execution in a multithreaded architecture http://www.hipeac.net/node/2167; 14000 euro.
· 2005-2009, Participation to Integrated Project (IP), Sixth Framework Program (FP6), Future and Emerging Technologies (FET), “SCALA/SARC: Scalable Architectures”, founding 8.5 M-EURO.
· 2004-2008, Coordinator of HiPEAC research cluster: Scalable Multicore Architectures, European Network of Excellence, Sixth Framework Program (FP6),in Cooperation with Universities of Goteborg-Chalmers (Sweden), Delft-TUD (Netherlands), Barcelona-UPC (Spain), founding 30 K-EURO.
· 2004-2008, Deputy Steering Committee, European Network of Excellence, Sixth Framework Program (FP6), “HIPEAC: High-Performance Embedded Architecture and Compilation”, coordination Polytechnic University of Catalonia, Spain (UPC), founding 3.9 M-EURO.
· 2004-2005, National Coordinator and Principal Investigator of project funded by Italian Investment Fund for Basic Research (FIRB), Italian Ministry of Education, University and Research (MIUR), “Innovative Architectures for High Performance Processors”, 60 K-EURO.
· 2004, Coordinator and Principal Investigator “Monte dei Paschi di Siena Foundation”, “Study and Realization of a Multimedia System for Translating and Communicating with the Sign Language for the Deaf”, 40 K-EURO.
· 2004-2005, Coordinator and Principal Investigator of project funded by University Research Plan (PAR) of the University of Siena, “Innovative Architectures for Multimedia Applications in Embedded Systems”, 15 K-EURO.
· 2003-2005, participation to project funded by Italian Investment Fund for Basic Research (FIRB), Italian Ministry of Education, University and Research (MIUR), “Reconfigurable Platforms for Broadband Mobile Devices”, activity of “Development of Innovative Cryptographic Techniques”, coordinator prof. Enrico Martinelli, 80 K-EURO.
RESEARCH THEMES AND SCIENTIFIC INTERESTS
Roberto Giorgi’s research themes are focused in the area of Computer System Architecture. Among them:
· Low-Power techniquies for Embedde Systems [C41,C40,C35,C33].
Nei sistemi embedded uno dei sottosistemi critici e’ la memoria cache, sia per le prestazioni, sia perche’ le sempre crescenti dimensioni generano importanti frazioni del consumo di potenza.
In particolare, le perdite (leakage) continuano ad essere un problema nonostante l’uso di materiali ad alta costante dielettrica (Hi-K) anche nelle tecnologie a 45nm, gia’ a temperature normali di esercizio (sopra i 30 gradi Celsius). Una proposta innovativa e’ data dall’effetto di filtraggio di uno stadio di cache non-a-basso-consumo preposto ad uno stadio di cache a-basso-consumo. Miglioramenti significativi possono essere cosi’ raggiunti a costi praticamente trascurabili in termini di area e complessita’ del progetto.
· Design techniques of embedded systems for mobile and multimedia applications: in particular, architectural support for cryptography [L1, J16, J14, J10, C24, C20].
I sistemi di crittografia basati su curve ellittiche (Elliptic Curve Cryptography o ECC) hanno il vantaggio di lavorare con operandi di lunghezza di almeno un ordine di grandezza inferiore rispetto a quella degli standard crittografici oggi comunemente in uso, quali RSA, DSA, Diffie-Helman, El-Gamal. Per questa importante caratteristica la crittografia basata sulle curve ellittiche è particolarmente adatta per l’impiego su smart-cards e dispositivi di tipo mobile ed embedded.
Tipicamente, vi sono due soluzioni possibili per migliorare le prestazioni dei sistemi ECC, la prima è l’ottimizzazione del software, la seconda è la realizzazione in hardware di coprocessori aritmetici. L’implementazione software è senza dubbio flessibile, ma le prestazioni che si otterrebbero nei dispositivi embedded sarebbero insufficienti; al contrario lavorare in hardware è costoso e non offre la flessibilità desiderata.
La ricerca effettuata, utilizzando come modello il set di istruzioni dei processori ARM, molto diffusi in applicazioni embedded, ha avuto risultati molto promettenti, individuando il supporto architetturale che comporti da un lato le minime modifiche hardware e dall’altro il massimo beneficio in termini di riduzione dei tempi di esecuzione e di riduzione delle risorse globalmente utilizzate.
· Evaluation and proposal of a new microprocessor architecture based on multithreading and dataflow concepts, which enables to overcome traditional limitations to Superscalars and VLIWs [C42,C38,C38,C37,C36, J13, J8, J7, J6, J6, C17, C12].
E’ stata analizzata la possibilita’ di utilizzare una nuova architettura di processore che si potesse distaccare in maniera sensibile dalle attuali architetture basate principalmente sui paradigmi Superscalari e VLIW. La ricerca ha portato alla definizione di un nuovo tipo di microprocessore che recupera i concetti di dataflow e li esprime pienamente applicandoli ai sistemi multithreaded (o multi-contesto). L’architettura prende il nome di Scheduled Data-Flow (SDF) e si inserisce nel contesto delle architetture che tendono a svincolare gli accessi alla memoria dal flusso principale del programma (Memory Decoupled Architecture).
Per completezza, si e’ reso necessario confrontare le prestazioni della architettura proposta con quelle concorrenti e soprattutto con quelle oggi prodotte commercialmente. E’ stato quindi realizzato un simulatore dell’architettura ed e’ stato modificato il back-end di un compilatore, al fine di utilizzare benchmark, scritti in linguaggio ad alto livello sulla nostra architettura sperimentale.
I risultati sono stati molto incoraggianti gia’ coi primi prototipi simulati e hanno dimostrato che questo tipo di architettura consente non solo di ottenere prestazioni superiori agli attuali processori superscalari, e VLIW, ma anche di sfruttare a pieno il parallelismo a livello di thread intrinsecamente presente nelle applicazioni, superando i limiti di scalabilita’ delle risorse interne al processore (es. limitato parallelismo a livello di istruzione), tipici delle attuali architetture.
· Study of original solutions to handle coherence of shared-bus and single-chip multiprocessor systems, for performance improvement of single- and multi-threaded hardware [J4, J2, J1, C10, C9, C7, C5, C2, C1, M2, M1].
In questo filone di ricerca si e’ proposto un nuovo protocollo di coerenza, denominato PSCR (Passive Shared Copy Removal), per sistemi multiprocessore a bus condiviso e memoria condivisa. Questo tipo di architettura risulta particolarmente attraente dato il suo basso costo e la semplicita’ implementativa. La necessita’ di introdurre la memoria cache al fine di alleggerire il traffico sul bus condiviso – collo di bottiglia per le prestazioni - comporta pero’ la generazione di ulteriore traffico per gestire la coerenza dei dati nelle varie cache. Tale traffico puo’condizionare pesantemente le prestazioni e la scalabilita’ del sistema, tanto che risulterebbe del tutto inutile costruire multiprocessori basati su questa architettura con piu’ di quattro processori. Il traffico di gestione della coerenza e’ pero’ composto anche da transazioni superflue, soprattutto per le applicazioni di uso generale (non-scientifiche o non-parallelizzabili) che costituiscono il motivo principale per cui una piattaforma di questo tipo viene utilizzata. Si e’ scoperto che tale traffico inutile e’ generato dalle copie di dati passivamente condivise, ovvero dalle copie di dati privati che appaiono erroneamente condivise perche’ il processo che le utilizza migra da un processore ad un altro. L’attivita’ di migrazione e’ altresì necessaria se si vuole mantenere un corretto bilanciamento del carico di processi fra i processori disponibili. La soluzione proposta interviene a livello di protocollo di coerenza e consente di eliminare completamente la condivisione passiva.
La scalabilita’ del sistema ottenibile adottando tale protocollo e’ stata confrontata con quella ottenibile con altri sei protocolli noti in letteratura o impiegati diffusamente, quali il protocollo MESI. I risultati hanno mostrato che con l’uso di PSCR, puo’ avere senso utilizzare l’architettura a bus comune per costruire multiprocessori a memoria condivisa fino a 24 processori. Tale soluzione e’ stata anche valutata nel caso di processori che al loro interno supportano piu’ contesti ottenendo, ancora una volta, risultati per PSCR migliori rispetto agli altri protocolli.
· Study of solutions for improving performance of multiprocessor system used as Web-Servers and Data-Base Management Systems (DBMS). In particular, process migration problems in the case of E-Commerce, On-Line Transaction Processing (OLTP) e Decision Support System (DSS) [J12, J11, J9, C21, C19, C16, C15, C14, C13, C11].
Web-Server e DBMS (Data Base Management System) sono sistemi particolarmente critici da un punto di vista delle prestazioni. Ad es. sistemi di E-Commerce, OLTP (On-Line Transaction Processing) e DSS (Decision Support System) sono implementati con un’architettura distribuita N-tier o anche semplicemente three-tier, nel cui secondo strato agisce principalmente un Web-Server e nel terzo strato agisce principalmente un DBMS (essendo il primo strato costituito dal client o Web-browser). Per far fronte ad un alto numero di richieste la soluzione tipica consiste nel ricorrere a Network di Workstations (o Clusters). Nei casi in cui il singolo nodo costituisca di per se’ un sistema multiprocessore (es. a bus-condiviso e memoria condivisa), si rende necessario ricorrere ad ogni possibile accorgimento per massimizzarne le prestazioni. In particolare, tenendo conto della struttura complessiva del sistema, il carico della macchina (workload) e’ costituita da un’intensa attivita’ multitasking (generata da richieste di Web-Clients e DB-Query nei due casi) che comporta un forte impegno del Sistema Operativo (e.g. Scheduler, Memoria Virtuale) nel bilanciamento del carico.
Utilizzando questa piattaforma si e’ cercato di evidenziare quelle soluzioni architetturali atte a migliorare nettamente le prestazioni della macchina. Tramite l’uso combinato di interventi di ristrutturazione dei dati del kernel, del sistema operativo, dello scheduler e del protocollo di coerenza e’ possibile anche raddoppiare le prestazioni di un sistema multiprocessore basato su questa piattaforma. La metodologia utilizzata ha fatto ricorso ad applicazioni realmente utilizzate e in particolare ai benchmark ampiamente diffusi TPC-W e TPC-D.
· Handheld Multimedial Devices for the Deaf [D1, D2, J15, C29, C27, C23].
Dall’analisi delle effettive necessita’ dei sordi, è emerso che essi preferiscono comunicare attraverso la lingua dei segni, poiche’ questa è percepita come la propria lingua madre e, di fatto, permette un’immediatezza di comunicazione altrimenti difficilmente ottenibile. Gli sviluppi attuali delle tecnologie informatiche e l’incremento della capacità elaborativa dei dispositivi portabili (in particolare telefoni cellulari, calcolatori palmari e altri dispositivi mobili) consentono di poter di pensare al progetto di ausili tecnologici in grado di effettuare la traduzione automatica in Lingua dei Segni. Cio’ nonostante i vincoli sul consumo energetico e la capacità di elaborazione di tali dispositivi ‑ tipiche dei sistemi embedded ‑ debbono essere affrontati appropriatamente per rendere possibile un’utilizzazione accettabile da parte della comunita’ dei sordomuti.
Nella fase iniziale del progetto sono stati studiate le caratteristiche di resa tridimensionale tramite soggetti animati sintetizzabili (avatar) e l’implementazione del dizionario in Lingua Italiana dei Segni (LIS), individuando molteplici ottimizzazioni del software in grado di rendere possibile il trasferimento su piattaforma multimediale embedded.
· Innovative cache design techniques based on 3D locality curves: in particular, for designing embedded systems and using in computer architecture education [J3, C22, C18, C8, C6, C4, C3]
I sistemi di elaborazione racchiudono al loro interno numerosi dettagli che non e’ possibile verificare direttamente. Sono stati realizzati pertanto degli strumenti sperimentali in grado da un lato di dischiudere l’interno del microprocessore e della memoria cache tramite una semplice interfaccia basata disponibile come servizio Web, dall’altro di monitorare l’attivita’ dello studente nelle varie parti dello strumento verificandone cosi’ l’utilizzazione.
COPYRIGHT and INTELLECTUAL PROPERTY
D2) [Bartolini06e]
S. Bartolini, P. Bennati, R. Giorgi, "BlueSign 2", SIAE
24-02-2006/001, Reg. 24 Feb. 2006.
D1) [Bennati03a]
P. Bennati, T. Capasso, V. Di Massa, F. Giallombardo, R. Giorgi, M.
Guerrini, E. Maggio , N. Nannetti, "BlueSign Translator", SIAE
002568, Ord. D003454, Reg.
21 Mar. 2003.
INTERNATIONAL JOURNALS
J16) [Bartolini08a]
S. Bartolini, I. Branovic, R. Giorgi, E.
Martinelli, "Effects of Instruction-set Extensions on an Embedded
Processor: a Case Study on Elliptic Curve Cryptography over GF(2/sup m/)",
IEEE Trans. Computers, ISSN:0018-9340, Los
Alamitos, CA, USA, vol. 57, no. 5, May 2008, pp. 672-685.
J15) [Bartolini07a]
S. Bartolini, P. Bennati, R. Giorgi, "L'Informatica per i sordi: su
palmare la lingua dei segni", Mondo Digitale, June 2007, pp. 42-49.
J14) [Bartolini06d]
S. Bartolini, P. Foglia, R. Giorgi, C. A. Prete,
"MEmory performance: DEaling with Applications, systems and
architecture", ACM SIGARCH Computer Architecture News,
ISSN:0163-5964, New York, NY, USA2, vol. 34, no. 1, Mar. 2006, pp. 1-2.
J13) [Bartolini06b]
S. Bartolini, R. Giorgi, "Issues in Embedded
Single-Chip Multicore Architectures", Journal of Embedded Computing,
ISSN:1740-4460, Amsterdam, Netherlands, vol. 2, no. 2, Dec. 2006, pp. 137-139.
J12) [Foglia05a]
P. Foglia, R. Giorgi, C. A. Prete, "Reducing coherence overhead and
boosting performance of high-end SMP multiprocessors running a DSS
workload", ELSEVIER Journal of Parallel and Distributed Computing,
ISSN:0743-7315, Amsterdam, Netherlands, vol. 65, no. 3, Mar. 2005, pp. 289-306.
J11) [Foglia04b]
P. Foglia, R. Giorgi, C. A. Prete,
"Speeding-up multiprocessors running DBMS workloads through coherence
protocol", Int. J. High Performance Computing and Networking, ,
ISSN:1740-0562, Olney, Bucks. (UK), vol. 1, no. 1/2, June 2004, pp. 17-32.
J10) [Branovic04b]
I. Branovic, R. Giorgi, E. Martinelli, "A
Workload Characterization of Elliptic Curve Cryptography Methods in Embedded
Environments", ACM SIGARCH Computer
Architecture News, ISSN:0163-5964, New York, NY, USA, vol. 32, no. 3, June 2004, pp. 27-34.
J9) [Foglia04a]
P. Foglia, R. Giorgi, C. A. Prete, "Simulation
Study of Memory Performance of SMP Multiprocessors Running a TPC-W
Workload", IEE Proceedings Computers and Digital Techniques,
ISSN:1350-2387, London, UK, vol. 151, no. 2, Mar. 2004, pp. 93-109.
J8) [Bartolini01a]
S. Bartolini, R. Giorgi, J. Protic, C. A. Prete ,
M. Valero, "Parallel Architecture and Compilation Techniques: Selection of
workshop papers, Guests' Editors Introduction", ACM SIGARCH Computer
Architecture News, ISSN:0163-5964, New York, NY, USA, vol. 29, no. 5,
Dec. 2001, pp. 9-12.
J7) [Kavi01a]
Krishna M. Kavi, Roberto Giorgi, Joseph Arul, "Scheduled Dataflow: Execution Paradigm, Architecture, and
Performance Evaluation", IEEE Trans. Computers,
ISSN:0018-9340, Los Alamitos, CA, USA, vol. 50, no. 8, Aug. 2001, pp. 834-846.
J6) [Giorgi01a]
R. Giorgi, "Memory Decoupled Architectures and related issues Guest
Editor's Introduction", IEEE TCCA Newsletter, ISSN:1041-1186
, Los Alamitos, CA, USA, Jan. 2001, pp. 2-4.
J5) [Kavi00a]
K. Kavi, J. Arul, R. Giorgi, "Execution and
Cache Performance of the Scheduled Dataflow Architecture", SPRINGER
Journal of Universal Computer Science, ISSN:0948-6968, New York, NY, (USA),
vol. 6, no. 10, Oct. 2000, pp. 948-967, Special Issue on Multithreaded
Processors and Chip Multiprocessors.
J4) [Giorgi99a]
Roberto Giorgi, Cosimo Antonio Prete, "PSCR: A Coherence Protocol for
Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors", IEEE
Trans. Parallel and Distributed Systems, Vol. 10, No. 7,
ISSN:1045-9219, Los Alamitos, CA, USA, July 1999, pp. 742-763.
J3) [Giorgi99c]
R. Giorgi, C.A. Prete, "An Educational
Environment for Designing and Performance Tuning of Embedded Systems", IEEE TCCA Newsletter, ISSN:1041-1186 , Los Alamitos , CA, USA, Feb. 1999, pp. 54-56.
J2) [Giorgi97e]
R. Giorgi, C.A. Prete, G. Prina, L. Ricciardi,
"Trace Factory: Generating Workloads for Trace-Driven Simulation of
Shared-Bus Multiprocessors", IEEE Concurrency,
ISSN:1092-3063, Los Alamitos, CA, USA, vol. 5, no. 4, Oct. 1997, pp. 54-68.
J1) [Prete97a]
C. A. Prete, G. Prina, R. Giorgi, L. Ricciardi,
"Some Considerations About Passive Sharing in Shared-Memory
Multiprocessors", IEEE TCCA Newsletter, ISSN:1041-1186, Los
Alamitos, CA, USA, Mar. 1997, pp. 34-40.
BOOK’S CHAPTERS
L1) [Bartolini08b]
S. Bartolini, R.
Giorgi, E. Martinelli, "Cryptographic Engineering", Springer, ISBN:978-0-387-71816-3,
2008, pp. 191-233.
BOOKS
E3) [Bartolini08c]
S. Bartolini, P.
Foglia, R. Giorgi, C. A. Prete, "MEDEA '08: Proc. 2008 workshop on MEmory
performance", ACM, ISBN:978-1-60558-243-6, New York, NY, USA, 2008, pp.
1-84.
E2) [Bartolini07c]
S. Bartolini, P. Foglia, R. Giorgi, C. A. Prete,
"MEDEA '07: Proc. 2007 workshop on MEmory performance", ACM,
ISBN:978-1-9593-807-7, New York, NY, USA, 2007, pp. 1-113.
E1) [Bartolini06f]
S. Bartolini, P. Foglia, R. Giorgi, C. A. Prete, "Proc. 2006 workshop
on MEmory performance: DEaling with Applications, systems and
architectures", ACM Press, ISBN:1-59593-568-1, New York, NY,
U.S.A., 2006, pp. 1-52.
CONFERENCE PROCEEDINGS
C42) [Giorgi09a]
R.
Giorgi, Z. Popovic, N. Puzovic, "Implementing hardware TLP support for the
Cell processor", Proc. IEEE
Int.l Workshop on Multi-Core Computing Systems, Fukuoka, Japan, Mar. 2009, pp. 1-6, (accepted for
publication).
C41) [Giorgi08a]
R. Giorgi, P. Bennati, "Filtering drowsy
instruction cache to achieve better efficiency", SAC
'08: Proc. 2008 ACM symposium on Applied computing,
ISBN:978-1-59593-753-7, New York, NY, USA, Mar. 2008, pp. 1554-1555.
C40) [Giorgi08e]
R.
Giorgi, P. Bennati, "Reducing Leakage through Filter Cache", Proc. 11th
IEEE EUROMICRO-DSD,
ISBN:978-1-59593-753-7, Parma, Italy, Sept.t 2008, pp. 334-341.
C39) [Giorgi08d]
R.
Giorgi, Z. Popovic, N. Puzovic, A. Azavedo and B. Juurlink, "Analyzing
Scalability of Deblocking Filter of H.264 via TLP exploitation in a new
many-core architecture", Proc. 11th
IEEE EUROMICRO-DSD,
ISBN:978-1-59593-753-7, Parma, Italy, Sept.t 2008, pp. 189-194. C38) [Giorgi08c]
R.
Giorgi, Z. Popovic, N. Puzovic, "Implementing DTA support in
CellSim", HiPEAC ACACES-2008, ISBN:978-90-382-1288-3, L'Aquila, Italy, July 2008, pp.
159-162.
C37) [Giorgi08b]
R. Giorgi, Z. Popovic, N. Puzovic, A. Azavedo
and B. Juurlink, "Exploiting Parallelism of Deblocking Filter of H.264 on
DTA architecture", HiPEAC ACACES-2008, ISBN:978-90-382-1288-3,
L'Aquila, Italy, July 2008, pp. 55-58.
C36) [Giorgi07a]
R. Giorgi, Z. Popovic, N. Puzovic, "DTA-C: A
Decoupled multi-Threaded Architecture for CMP Systems", Proc. IEEE
SBAC-PAD, ISBN:0-7695-23014-1, Gramado, Brasil, Oct. 2007, pp. 263-270.
C35) [Giorgi07b]
R. Giorgi, P. Bennati, "Reducing leakage in power-saving capable
caches for embedded systems by using a filter cache", Proc. ACM
MEDEA, ISBN:978-1-59593-807-7, Brasov, Romania, Sept. 2007, pp.
105-112.
C34) [Giorgi07c]
R. Giorgi, Z. Popovic, N. Puzovic, "Decoupled Threaded
Architecture", HiPEAC ACACES-2007, ISBN:97-890-382-1127-5,
L'Aquila, Italy, July 2007, pp. 119-121.
C33) [Bennati07a]
P. Bennati, R. Giorgi, "Adaptive Cache Decay", HiPEAC
ACACES-2007, ISBN:97-890-382-1127-5, L'Aquila, Italy, July 2007, pp. 1-4.
C32) [Giorgi06b]
R. Giorgi, N. Puzovic, "Scheduling and NoC Traffic Reduction in T-SDF
Architecture", HiPEAC ACACES-2006, ISBN:90-382-0981-9, L'Aquila,
Italy, July 2006, pp. 253-256.
C31) [Giorgi06a]
R. Giorgi, Z. Popovic, "Core Design and Scalability of Tiled SDF
Architecture", HiPEAC ACACES-2006, ISBN:90-382-0981-9, L'Aquila,
Italy2, July 2006, pp. 145-148.
C30) [Bennati06a]
P. Bennati, R. Giorgi, "JCacheSim: simulatore visuale di gerarchia di
memoria con interprete per programmi MIPS", AICA Didamatica,
Cagliari, Italy, May 2006, pp. 105-114.
C29) [Bartolini06c]
S. Bartolini, P. Bennati, R. Giorgi, "BLUESIGN: traduttore
multimediale portatile per non udenti", AICA Didamatica, Cagliari,
Italy, May 2006, pp. 17-24.
C28) [Bartolini06a]
S. Bartolini, P. Bennati, R. Giorgi, E. Martinelli,
"Elliptic Curve Cryptography support for ARM based Embedded systems",
HiPEAC ACACES-2006, ISBN:90-382-0981-9, L'Aquila, Italy, July 2006, pp.
13-16.
C27) [Bartolini05c]
S. Bartolini, P. Bennati, R. Giorgi, "Bluesign-2, il nuovo
visualizzatore portatile per la Lingua Italiana dei Segni", Atti del
51esimo Convegno Nazionale di Studio ed Aggiornamento AIES, S. Pellegrino
(BG), Italy, Aug. 2005, pp. 140-145.
C26) [Bartolini05b]
S. Bartolini, R. Giorgi, E. Martinelli, Z. Popovic,
"Recent Proposals for Tiled Architectures", HiPEAC ACACES-2005,
ISBN:90-382-0802-2, L'Aquila, Italy, July 2005, pp. 47-50.
C25) [Alioto05a]
M. Alioto, S. Bartolini, P. Bennati, R. Giorgi, "New techniques for
low power caches", HiPEAC ACACES-2005, ISBN:90-382-0802-2,
L'Aquila, Italy, July 2005, pp. 133-136.
C24) [Bartolini04a]
S. Bartolini, I. Branovic, R. Giorgi, E. Martinelli, "A Performance
Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary
Finite Fields", IEEE 16th Symp. on Computer Architecture and High
Performance Computing (SBAC-PAD-04), ISBN:0-7695-2240-8,
ISSN:1550-6533, Foz do Iguacu, Brasil, Oct. 2004, pp. 238-245.
C23) [Bartolini04b]
S. Bartolini, P. Bennati, R. Giorgi, "Sistema per la traduzione in
Lingua Italiana dei Segni: Blue Sign Translator / Wireless Sign System", Atti
del 50esimo Convegno Nazionale di Studio ed Aggiornamento AIES, Chianciano
Terme - Siena, Italy, Aug. 2004, pp. 203-212.
C22) [Branovic04a]
I. Branovic, R. Giorgi, E. Martinelli,
"WebMIPS: A New Web-Based MIPS Simulation Environment for Computer
Architecture Education.", IEEE Workshop on Computer Architecture
Education (WCAE-04), Munich, Germany, June 2004, pp. 93-98.
C21) [Foglia03a]
P. Foglia, R. Giorgi, C.A. Prete, "Speeding-up
Multiprocessors Running DSS Workloads through Coherence Protocols", 2nd
Workshop on Hardware Software Support for Parallel and Distributed Scientific
and Engineering Computing (SHPSEC-03), New Orleans, LA, USA, Sept. 2003, pp. 124-149.
C20) [Branovic03a]
I. Branovic, R. Giorgi, E. Martinelli, "Memory
Performance of Public-Key cryptography Methods in Mobile Environments", ACM
SIGARCH Workshop on MEmory performance: DEaling with Applications, systems and
architecture (MEDEA-03), New Orleans, LA, USA, Sept. 2003, pp. 24-31.
C19) [Foglia02a]
Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete, "Boosting the Performance of Three-Tier Web Servers Deploying SMP
Architecture", Springer-Verlag LNCS Workshop on Web Engineering (WWE-02),
ISBN:3-540-44177-8, Pisa, Italy, vol. 2376, May 2002, pp. 134-146.
C18) [Branovic02a]
I. Branovic, R. Giorgi, C.A. Prete, "Web-based
training on Computer Architecture: The case for JCachesim", IEEE
Workshop on Computer Architecture Education (WCAE-02), Anchorage, AK, USA, May 2002, pp. 56-60.
C17) [Kavi01b]
K. Kavi, J. Arul, R. Giorgi, "Performance Evaluation of a Non-Blocking
Multithreaded Architecture for Embedded, Real-Time and DSP Applications", 14th
Int.l Conf. on Parallel and Distributed Computing Systems (ISCA-PDCS-01),
ISBN:1-880843-39-0, Richardson, TX, USA, Aug. 2001, pp. 365-371.
C16) [Foglia01e]
P. Foglia, R. Giorgi, C.A. Prete, "OS Effects
on Memory Hierarchy of a SMP Multiprocessor Running a DBMS Workload", Int.l
Conf. on Advances in Infrastructure for E-Business, Science, and Education
(SSGRR-01), ISBN:88-85280-61-7, L'Aquila, Italy, Aug. 2001, pp. 1-8
(cdrom).
C15) [Foglia01d]
P. Foglia, R. Giorgi, C. Prete, "Accelerating DSS Workloads through Coherence Protocols", ACM
Workshop on Caching and Coherence Consistency (WC3-01), Sorrento, Italy, June 2001, pp. G.1-G.8.
C14) [Foglia01c]
P. Foglia, R. Giorgi, C.A. Prete, "Performance
Analysis of Parallel Applications Running on SMP", Int.l Conf. on
Parallel and Distributed Processing Techniques and Applications (PDPTA-01),
ISBN:1-892512-70-X, Las Vegas, NV, USA, vol. IV, June 2001, pp. 1634-1640.
C13) [Foglia01a]
P. Foglia, R. Giorgi, C. Prete, "Evaluating Optimizing for Multiprocessors E-Commerce Server Running
TPC-W Workload", IEEE Proc. 34th Annual Hawaii Int.l Conf. on System
Sciences (HICSS-34), ISBN:0-7695-0981-9, Maui, Hawaii, USA, vol. 7, Jan. 2001, pp. 2544-2552.
C12) [Kavi00b]
K. Kavi, R. Giorgi, J. Arul, "Comparing
Execution Performance of Scheduled Dataflow Architecture with RISC
Processors", Proc. 13th ISCA Parallel and Distributed Computing Systems
Conf. (ISCA-PDCS-00),
ISBN:1-880843-34-X, Las Vegas, NV, USA, Aug. 2000, pp. 41-47.
C11) [Foglia00a]
P. Foglia, R. Giorgi, C.A. Prete, "Performance Analysis of Electronic Commerce
Multiprocessor Servers", IEEE Proc. 33th Annual Hawaii Int.l Conf.
on System Sciences (HICSS-33), ISBN:0-7695-0493-0, Maui, Hawaii, USA, Jan. 2000, pp. 2214-2222.
C10) [Foglia99a]
P. Foglia, R. Giorgi, C.A. Prete, "Process Migration Effects on Memory
Performance of Multiprocessor Web-Server", Springer-Verlag LNCS
Proc. High Performance Computing Conf. (HIPC-99), ISBN:3-540-66907-8, Calcutta, India, vol. 1745, Dec. 1999, pp. 133-142.
C9) [Giorgi99d]
R. Giorgi, C.A. Prete, "A Coherence Protocol
for the Elimination of Passive Sharing in Single and Multiple Threaded
Shared-Bus Shared-Memory Multiprocessors", Eighth Workshop on Scalable
Shared Memory Multiprocessors (WSSMM-99), Atlanta, Georgia, May 1999, pp.
29.
C8) [Giorgi98b]
R. Giorgi, C.A. Prete, "An Educational
Environment for Designing and Performance Tuning of Embedded Systems", IEEE
Workshop on Computer Architecture Education (WCAE-98), Barcelona, Spain, June 1998, pp. VII/A.1-6.
C7) [Foglia98a]
P. Foglia, R. Giorgi, C.A. Prete, "Analysis of
Sharing Overhead in Shared Memory Multiprocessors", IEEE Proc. 31st
Annual Hawaii Int.l Conf. on System Sciences (HICSS-31),
ISBN:0-8186-8255-8, Big Island, Hawaii, USA, vol. 7, Jan. 1998, pp. 776-777.
C6) [Giorgi97f]
R. Giorgi, C.A. Prete, G. Prina, "An Educational
Environment for Program Behavior Analysis and Cache Memory Design", IEEE
Proceedings Int.l Conf. on Frontiers in Education (FIE-97),
ISBN:0-7803-4086, Pittsburgh, PA, USA, Nov. 1997, pp. 1243-1248.
C5) [Giorgi97c]
R. Giorgi, P. Foglia, C.A. Prete, "Bus Utilization Analysis of
Multithreaded Shared-Bus Multiprocessors: Initial Results", IASTED
Proc. 9th Int.l Conf. on Parallel and Distributed Computing and Systems
(IPDCS-97), ISBN:0-88986-240-0, Washington, DC, USA, Oct. 1997, pp. 24-29.
C4) [Giorgi97b]
R. Giorgi, C.A. Prete, G. Prina, "Cache Memory
Design for Embedded Systems Based on Program Locality Analysis", IEEE
Proc. Int.l Conf. on Microelectronic System Education (MSE-97),
ISBN:0-8186-7996-4, Arlington, VA, USA, July 1997, pp. 16-18.
C3) [Giorgi97d]
R. Giorgi, C.A. Prete, G. Prina, "An approach
for investigating design and tuning performance of embedded systems", EAEEIE
Proc. Int.l Conf. on Innovation and Quality in Education for Electrical and
Information Engineering, Edinburgh, Scotland, UK, June 1997, pp. G1.15-20.
C2) [Giorgi97a]
R. Giorgi, C.A. Prete, G. Prina, L. Ricciardi,
"A Workload Generation Environment for Trace-Driven Simulation of
Shared-Bus Multiprocessor", IEEE Proc. 30th Hawaii Int.l Conf. on
System Sciences (HICSS-30), ISBN:0-8186-7734-1, Maui, Hawaii, vol. 1,
Jan. 1997, pp. 266-275, Best mini-track paper award.
C1) [Giorgi96a]
R. Giorgi, C.A. Prete, G. Prina, L. Ricciardi,
"A Hybrid Approach to Trace Generation for Performance Evaluation of
Shared-Bus Multiprocessors", IEEE Proc. 22nd EuroMicro Int.l Conf. (EM-96),
ISBN:0-8186-7487-3, Prague, Ceck Republic, Sept. 1996, pp. 207-214.
MISCELLANEOUS
M6) [Giorgi07d]
R. Giorgi, Z. Popovic, N. Puzovic, "Memory
access decoupling in a multithreaded architecture", WIRTES 2007 - Primo
Workshop Italiano su Real-Time Embedded Systems, Pisa, Italy, July 2007,
pp. 1-11.
M5) [Bartolini05b]
S. Bartolini, R. Giorgi, E. Martinelli, Z. Popovic, "Recent Proposals
for Tiled Architectures", Poster Abstract of the HiPEAC ACACES-2005 Summer
School, Academia Press, ISBN: 90-382-0802-2, 2005, pp. 47-50.
M4) [Alioto05a]
M. Alioto, S. Bartolini, P. Bennati, R. Giorgi,
"New Techniques for low power caches", Poster Abstract of the HiPEAC
ACACES-2005 Summer School, Academia Press, ISBN: 90-382-0802-2, 2005, pp.
133-136.
M3) [Bartolini05a]
S. Bartolini, R. Giorgi, E. Martinelli, Z. Popovic,
"Tiled Architectures & Recent Proposals for Chip
Multiprocessors", Technical Report n.2005-4 DII-UNISI, Siena, May 2005.
M2) [Giorgi99b]
Roberto Giorgi,
"Evaluation of a Coherence Protocol for Eliminating Passive Sharing in
Shared-Bus Multithreaded Multiprocessors", University of Pisa, Dept. Ingegneria
della Informazione, Ph.D. Thesis, Pisa, Italy, Jan. 1999, pp. 84.
M1) [Giorgi95a]
Roberto Giorgi, "Trace
Driven Performance Evaluation of Multiprocessors ", University of Pisa,
Dept. Ingegneria della Informazione, MS Thesis, Pisa, Italy,
July 1995, pp. 84.
Seminars and Talks
·
2005, May 11: “Tiled Architectures for Embedded
Systems”, Department of
Electronics and Information Systems, Ghent, Belgio.
· 2004, October 7: “Non- Conventional Microprocessor Architectures”, Department of Computer Engineering, Delft, Olanda.
· 2004, September 30: “Embedded-System Research Overview”, HiPEAC Workshop, Juan les Pins, Francia.
· 2003, 7 Novembre: “Non-Convential Microprocessor Architectures”, incontro con StarCore LLC e Facolta’ di Ingegneria dell’Universita’ di Pisa, Pisa.
· 2002, 25 Gennaio: “Non-Convential Microprocessor Architectures”, Keynote Speech, SSGRRw-2002 Conference, L’Aquila.
· 2001, 9 Novembre: “Architetture Non-Convenzionali per Microprocessore”, SGS-Thomson Advanced Research Laboratory, Milano.
· 2000, 2 Aprile: “Introduzione alla Architettura Scheduled Data-Flow -SDF”, Dipartimento di Ingegneria dell’Informazione, Università di Siena.
· 1999, 15 Maggio: Scheduled Dataflow Architecture: problems and issues”, Department of Electrical and Computer Engineering, University of Alabama in Huntsville, AL, USA.
· 1998, 7-8 Maggio: “Simulating Composite Workloads on Shared-Bus Symmetric Multiprocessors”, University of Belgrade, Serbia, Yugoslavia.
· 1997, 9 Settembre: “Trace Factory: a Hybrid Approach to Trace Generation for Performance Evaluation of Shared Bus Multiprocessors”, Scuola GII, Facolta’ di Ingegneria, Università di Salerno, Benevento.
· 1997, 4 Agosto: “Trace Driven Simulation of Shared-Bus Multiprocessors”, Computer Science and Engineering Department, University of Texas at Arlington, TX, USA.