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 INTRODUCTION
This project aims to explore a new design space in processor architecture to exploit untapped sources of parallelism available in programs.
Current processor architectures are based on Superscalar, Superspeculative and Very Long Instruction Word (VLIW, e.g. Intel/Itanium) paradigm.
This trend permits for better performance at the expense of greater hardware complexity, and without coping directly with the problem of the natural flow of data.
In this project, we are exploring new architectural paradigms partially based on the concepts of dataflow and multitrading to obtain
a much faster execution time. We wish to explore possible application of this architecture to embedded systems, expecially
in the case of multimedia and cryptographic applications.
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PRESENTATIONS
2004, October 7: "Non- Conventional Microprocessor Architectures", Department of Computer Engineering, Delft, The Netherlands.
2004, September 30: "Embedded-System Research Overview", HiPEAC Workshop, Juan les Pins, France.
2003, November 7: "Non-Conventional Microprocessor Architectures", meeting with StarCore LLC and Faculty of Engineering, University of Pisa, Pisa, Italy.
2002, January 25: "Non- Conventional Microprocessor Architectures", Keynote Speech, SSGRRw-2002 Conference, L'Aquila, Italy.
2001, November 9: "Non- Conventional Microprocessor", ST-Microelectronics, Advanced Research Laboratory, Milan, Italy.
ST-Microelectornics, Advanced System Technology Lab, Agrate, Italy, .
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PUBLICATIONS
S. Bartolini and C. A. Prete, "Optimizing instruction cache performance of embedded systems", Trans. on Embedded Computing Sys. 4, 4 (Nov. 2005), 934-965, ISSN: 1539-9087. DOI= http://doi.acm.org/10.1145/1113830.1113839
P. Foglia, D. Mangano, C. A. Prete, "A Cache Design for High Performance Embedded Systems", Journal of Embedded Computing (JEC), Vol. 1, Issue 4, 2005, ISSN: 1740-4460.
P. Foglia, D. Mangano, C. A. Prete, "A NUCA Model for Embedded Systems Cache Design", IEEE 2005 Workshop on Embedded Systems for Real-Time Multimedia (ESTIMEDIA), New York Metropolitan Area, Usa, September 2005, ISBN: 0-7803-9347-3.
P. Foglia, D. Mangano, C. A. Prete, "Tuning D-NUCA cache", Proceedings of the Poster Session of the 1st International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems ( ACACES2005), L\'Aquila, Italy, July 2005, ISBN: 90-382-0802-2.
S. Bartolini, P. Foglia, C. A. Prete, MEDEA04 Workshop Guests Editors\' Introduction, ACM SIGARCH Computer Architecture News , Vol. 33, Issue3, pp. 1-3, June 2005, ISSN:0163-5964.
M.Alioto, S. Bartolini, P. Bennati, R. Giorgi, "New Techniques for low
power caches", Poster Abstract of the HiPEAC ACACES-2005 Summer School,
Academia Press, ISBN: 90-382-0802-2, 2005, pp. 133-136.
S. Bartolini, R. Giorgi, E. Martinelli, Z. Popovic, "Recent Proposals for
Tiled Architectures", Poster Abstract of the HiPEAC ACACES-2005 Summer
School, Academia Press, ISBN: 90-382-0802-2, 2005, pp. 47-50.
S. Bartolini, R. Giorgi, E. Martinelli, Z. Popovic, "Tiled Architectures & Recent Proposals for Chip Multiprocessors", Technical Report n.2005-4 DII-UNISI, Siena, May 2005.
S. Bartolini and C. A. Prete, "A proposal for input sensitivity analysis of profile-driven optimizations on
embedded applications", SIGARCH Comput. Archit. News, ACM press, vol. 32, no.3, ISSN: 0163-5964, pp. 70--77, 2004.
S. Bartolini, I. Branovic, R. Giorgi, E. Martinelli, "A
Performance Evaluation of ARM ISA Extension for Elliptic
Curve Cryptography over Binary Finite Fields", IEEE 16th
Symp. on Computer Architecture and High Performance
Computing (SBAC-PAD-04), ISBN: 0-7695-2240-8,ISSN:1550-6533, Foz do Iguacu, Brasil, Oct. 2004, pp.
238-245.
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PEOPLE
NATIONAL COORDINATOR AND SIENA-UNIT RESPONSABLE:
Roberto Giorgi (email: see homeage), Principal Investigator, University of Siena,
PISA-UNIT RESPONSABLE:
Cosimo Antonio Prete, (prete@iet.unipi.it), University of Pisa,
COLLABORATORS:
Enrico Martinelli, (first_name@dii.unisi.it), University of Siena,
Sandro Bartolini, (last_name@dii.unisi.it), University of Siena,
Irina Branovic, (last_name@dii.unisi.it), University of Siena,
Zdravco Popovic, (last_name@dii.unisi.it), University of Siena,
Nikola Puzovic, (last_name@dii.unisi.it), University of Siena,
Paolo Bennati, (last_name@dii.unisi.it), University of Siena,
Pierfrancesco Foglia, (last_name@iet.unipi.it)University of Pisa.
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FUNDING
This project is funded by the Italian Ministry for the Education and the University (MIUR) as a FIRB project (special Italian Funding for Basic Research).
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